IP Verification Engineer – UVM / Scoreboards / System Verilog

IP Verification Engineer – UVM / Scoreboards / System Verilog

LONG TERM CONTRACT  

Exciting opportunity to work for a world leading electronics company in their leading lab located in Lund.

As an IP Verification Engineer you will work in a team developing serdes subsystem and it’s IPs for the company’s ASICs. Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.

As an IP Verification Engineer responsibilities will include;

• With a strong UVM background you will work on the development of UVM testbenches and test cases for IP.
• Debugging of test environment and design
• Creation of scoreboards
• Creation of relevant documentation

As an IP Verification Engineer your skills will include;

• Prior experience working in IP Verification role.
• Advanced user of System Verilog
• Advanced with UVM tools for IP Verification
• Experience in assertions, scoreboards and coverage refinement

Please send a CV attached to your application or email me at os@eu-recruit.com

IP Verification Engineer – UVM / Scoreboards / System Verilog

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