AMS (Analog-Mixed Signal) Verification Engineer

AMS (Analog-Mixed Signal) Verification Engineer (6 – 12 month contract)

You will be part of this Semiconductor companies Automotive Ethernet Verification team.

Responsibilities

• Verification Engineer (UVM) for Mixed Signal IP development; specify, execute and report Verification simulations of IP to proof the functional, structural and performance compliance before IC Mask Ordering.
• Define and apply verification test-cases, debug simulations, provide coverage reporting.

Requirements

• At least 5 years of working experience in AMS IC Design/Verification and a master degree (or similar level acquired by experience) in electronics or information engineering.
• Experience with state-of-art digital verification methodologies is required; UVM, system Verilog, coverage driven, assertions;
• Experience with Analog Mixed signal design/verification/modelling is preferred.
• knowledge of AMS IC development process, flows and IC application is preferred.
• Good skills in Verilog (AMS), UVM, System Verilog and/or VHDL, Tcl and/or Perl, Python, Linux/Unix scripting,
• Experience with SystemC, XML, Cadence EDA tooling is a plus!

Hourly rate negotiable – depends on experience of candidate. 

Tagged as: AMS, System verilog, UVM, Verification, Verilog