ASIC Digital Design Engineer – RTL / ASIC / Verilog

ASIC Digital Design Engineer
Opportunity to grow with a global technology company with R&D sites across Europe – looking for ASIC / IC Digital Design Engineers of all seniority levels to join them in Leuven, Belgium.

Responsibilities:
Close interface to the Arch and System S/W teams
Block and system specification through to timing-clean Verilog RTL

Skills:
Writing RTL
ASIC / IC Digital Design
Subsystem Design/ Implementation
Knowledge of top level verification: UVM,VMM,OVM
RTL, VHDL / Verilog, System Verilog
Knowledge of DSP Algorithms would be a big PLUS (but no a neccesity)

If this is of interest then please get in touch and we can discuss: lg@eu-recruit.com

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