Design Verification Engineer – CONTRACT – RTL / Verilog / IP / SoC / ASIC / FPGA

Design Verification Engineer – CONTRACT – RTL / Verilog / IP / SoC / ASIC / FPGA

Design Verification Engineer – RTL / Verilog / IP / SoC / ASIC / FPGA

I am searching for RTL Designers and Verification Engineers on a 6-month initial contract/

We are looking for driven engineers who have over 6 years’ expertise in RTL Design, IPs or SoC, HPC

Requirements

  • MSc or PhD in EE, computer Engineering etc.
  • 6+ years in Verilog or VHDL RTL Design or Verilog, System Verilog and Verification IPs
  • Scripting languages such as Python, TCL, Cshell etc.
  • Background in Circuit design is beneficial
  • Must have relevant work permissions for Sweden.

Key words: #Verification / #RTLDesign / #Semiconductors / #Hardware / IPs / SoC / ASIC / FPGA / RTL / VHDL / Verilog / System Verilog / PCIe High-Speed / Serdes / PHY

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