Digital Verification Engineer – 50% REMOTE – UVM

Website European Recruitment

Digital Verification Engineer – UVM, Block/SOC level

Are you looking for your next exciting challenge? Our globally-renowned semiconductor client is looking for an experienced digital verification engineer to join their site in Hamburg, Germany. 


You will be working with UVM and System Verilog technologies on formal verification for block and soc level. 50% REMOTE WORKING IS POSSIBLE. 


Key skills required for this Digital Verification Engineer role include: 


  • Relevant degree in electrical engineering or similar 
  • At least 5 years experience with Digital Verification
  • Expertice with UVM, Verilog and System Verilog 
  • Experience with Formal Verification



If you are interested in this Digital Verification position, apply directly to this advert or email me at

Keywords: Digital Verification, UVM, ASIC, FPGA, RTL, SOC, Verilog, System Verilog, OVM, EDA,  Formal Verification, Block Level Verification, Soc Level Verification, Semiconductors, IP, IC, Integrated Circuits


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Categories: Semiconductor & Electronics

  Salary: Negotiable

  Location: Hamburg, Germany

  Job type: Permanent, Full Time