Digital Verification Engineer – UVM/System Verilog/IP

Website European Recruitment

Digital Verification Engineer – UVM/System Verilog/IP 


Are you looking for your next exciting challenge? Our globally-renowned semiconductor client is looking for experienced digital verification engineersto join their site in Lund Hamburg.


You will be working with UVM and System Verilog technologies on formal verification/system level verification for IP/SoC.


Key skills required for this Digital Verification Engineer role include: 


  • Relevant master’s degree in electrical engineering or similar 
  • At least 5 years experience with Digital Verification
  • Expert in System Verilog 
  • Expert in UVM for IP Verification
  • Experience with Formal Verification and system level verification
  • Strong porgramming and scripting skills



If you are interested in this Digital Verification Engeerin position, apply directly to this advert or email me at

Keywords: Digital Verification, UVM, ASIC, FPGA, RTL, SOC, Verilog, System Verilog, OVM, EDA,  Formal Verification, Block Level Verification, Soc Level Verification, Semiconductors, IP, IC, Integrated Circuits, VHDL, TCL, Perl, Python


By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice

Categories: Semiconductor & Electronics

  Salary: Negotiable

  Location: Lund, Sweden

  Job type: Permanent, Full Time