Digital Verification Technical Leader – (Verilog, SystemVerilog, UVM)
Our client are looking to hire Digital VerificationTechnical leader to own the digital functional verification of our mixed-signal circuit designs in automotive platforms.
You will be responsible for:
- Studying the specification of the device under test
- Defining the test specification in closed collaboration with design leaders, verification architect and product definers
- Defining the digital verification planning to reach 100% functional coverage prior tapeout
- Developing the UVM simulation environment (drivers, monitors, checkers and assertions) and bridge it with mixed signal verification
- Developing and running digital and top-level simulations according to the verification plan
- Reporting bugs, proposing solutions and following their resolution
- Mentoring verification engineers on UVM methodology implementation
- Leading digital verification team on projects
You will work closely with analog and digital designers as well as test and validation engineers to support both pre-silicon verification and post-silicon validation. This is an opportunity for a skilled verification engineer to take the next step into leadership.
- Strong experience on digital verification methodologies (MDV, formal)
- Strong exp writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews
- Understand and debug digital RTL
- Knowledge of state of the art EDA tools: Cadence Incisive, Cadence Vmanager
- Strong background in Verilog, SystemVerilog, UVM, SVA.
- Exp in configuration database management (DesignSync, Git, SVN)
- Solid scripting skills
- Extensive exp verifying digital or mixed-signal ASICs
#Wireless & IoT
By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/