FPGA Back-End

FPGA Physical Design (Back-end) Engineer using (STA, SYNTHESIS, FLOOR PLANNING, VHDL)

Based in Sweden.

We are now hiring for an FPGA Physical Design (Back-end) Engineer using (STA, SYNTHESIS, FLOOR PLANNING, VHDL) – The successful candidate will join their expanding office, in Sweden. 

This will be on a rolling 6 month contract however the management team are very much looking for a long term candidate for this role so the likelihood of being extended is very high, considering the project has been funded for the next 3 years (minimum). 

Experience in the following;

• 3+ years in FPGA 
• FPGA Synthesis 
• Timing Closure for high-frequency FPGA Designs
• STA
• VHDL and verilog Source Code
• FPGA Floor Planning 
• Timing Contraints Development

FPGA Back-end Engineer job.

Key Words: FPGA / Physical Design / Backend / Back-end / Back end / Engineer / Engineer / STA / Synthesis / STA / VHDL

FPGA Physical Design (Back-end) Engineer using (STA, SYNTHESIS, FLOOR PLANNING, VHDL)

Tagged as: BS, Engineer, MS, Physical, Physical Design Engineer, STA, Synthesis

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