IC Verification Engineer (UVM)

We are looking for a IC Digital Verification Engineer to work with a leading semiconductor company specializing in the design and production of ultra low power, low voltage IC’s.

These IC’s are being used in consumer, automotive and industrial markets.

What are the responsibilities in this IC Digital Verification role?

Our client is looking for an IC digital verification engineer to strengthen the verification methodology development. You will also have interaction with the customer and production support team.

Other responsibilities include:

• Performing state of the art ultra low power IC verification, in a UVM methodology (SystemVerilog)
• Generate the industrial test patterns base on functional pattern
• Colloborate with other sites in US and Switzerland to improve synergy on methodology and share best practives
• Develop the verification strategy, test benches architecture and models

What are the requirements for this IC Digital Verification role?

• 3-5 years of work experience and preferrably in semiconductor industry
• Proven track record in digital verification methodologies of IC’s including testbench architecture, script writing, scoreboard and coverage methodology
• Knowledge of all digital verification steps (RTL, gate level)
• Knowledge of UVM methodology System Verilog (class approach) and VHDL
• Analog modelling is a plus but not essential
• C++ and or python is a plus 

Due to the urgency of this position we are not able to consider candidates outside the EU. If this sounds like a position you could be interested in please send on your CV to jthompson@eu-recruit.com.

#LI-JT1