Principal Analog Design Engineer – PMIC / Mixed Signal / CMOS / BCD

Principal Analog Design Engineer – PMIC / Mixed Signal / CMOS / BCD

  • Carinthia
  • Applications have closed

Principal Analog Design Engineer – PMIC / Mixed Signal / CMOS / BCD

We are looking for a Principal level Analog / Mixed Signal Design Engineer to join a client in Southern Austria, working on the design and verification of current and next-generation Power Management ICs.

You will be an industry expert in this field, and will continue to pursue excellence in your career in working on the most in-depth technological problems.

In this role you will act as a chip lead, coordinating teams working on power IC development, and contributing to the analog/mixed-signal IC design and verification from product definition through to production.

Key Requirements Include:

  • 10-15+ years experience in this field – analog/mixed-signal design and verification
  • Specific experience in Power Management / PMIC
  • Strong knowledge and experience with relevant IC development tools – Cadence, Synopsys etc.
  • Strong knoweldge of CMOS and/or BCD technologies

If you are interested in this Principal Analog Design Engineer role then please apply now with an up to date CV.

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)

Upload your CV/resume or any other relevant file. Max. file size: 100 MB.


You can apply to this job and others using your online resume. Click the link below to submit your online resume and email your application to this employer.

Access document

Case Studies

Quick Drop Your CV

A member of our team will contact you ASAP.

This is the heading

Lorem ipsum dolor sit amet consectetur adipiscing elit dolor

Send A New Vacancy

A member of our team will contact you ASAP.

This site uses cookies. Please accept our terms or find out more:

Please select your language: