RTL Design Engineer – SystemVerilog / Floating-point / Synthesis

RTL Design Engineer – SystemVerilog / Floating-point / Synthesis

  • Permanent, Full Time
  • London, UK

RTL Design Engineer – SystemVerilog / Floating-point / Synthesis

My client is a global leader in next-generation semiconductor and AI technology. They are looking to continue growing throughout 2021 and looking for experienced RTL Design Engineers.

Responsibilities for RTL Design Engineer:

  • Microarchitecture documentation
  • RTL implementation
  • Providing feedback to architecture, verification and physical design teams
  • Providing support for Verification debug and physical implementation
  • Maintaining good communication across teams and sites

 

Requirements for RTL Design Engineer:

  • Be highly motivated, a self-starter, and a team player
  • Ability to work across teams and debugging issues seen to find root causes
  • Python, Tcl

 

Interested to know more about this opportunity?

Please apply or email directly to jd@eu-recruit.com.

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/) 

Upload your CV/resume or any other relevant file. Max. file size: 50 MB.


You can apply to this job and others using your online resume. Click the link below to submit your online resume and email your application to this employer.

Access document

Download Info Pack

Access document

Case Studies

Quick Drop Your CV

A member of our team will contact you ASAP.

Send A New Vacancy

A member of our team will contact you ASAP.

Request A Callback

A member of our team will contact you ASAP.

This site uses cookies. Please accept our terms or find out more:

Please select your language: