RTL Design Engineer – SystemVerilog / Floating-point / Synthesis

RTL Design Engineer – SystemVerilog / Floating-point / Synthesis

My client is a global leader in next-generation semiconductor and AI technology. They are looking to continue growing throughout 2021 and looking for experienced RTL Design Engineers.

Responsibilities for RTL Design Engineer:

• Microarchitecture documentation
• RTL implementation
• Providing feedback to architecture, verification and physical design teams
• Providing support for Verification debug and physical implementation
• Maintaining good communication across teams and sites

Requirements for RTL Design Engineer:

• Be highly motivated, a self-starter, and a team player
• Ability to work across teams and debugging issues seen to find root causes
• Python, Tcl

Interested to know more about this opportunity?

Please apply or email directly to jd@eu-recruit.com.

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