Senior Design Verification Engineer

Our Client is a European leader in the semiconductor industry, now looking to expand their teams in the US. 

Specifically, they are looking or an experienced Design Verification Engineer to join their team in Plano, Texas.

Responsibilities

·     Responsible for design verification and validation of integrated circuits, using both directed tests and constrained random regressions

·     Primary focus is on digital design verification, but proficiency with mixed signal design verification and creation / validation of models are strong advantages

·     Creation of test benches and automated verification simulations

Requirements

– 10 Years Experience with IC Design Verification

– Experience with Mixed-Signal or Digital IC Verification

– Good knowledge of ASIC / FPGA design, verification and fabrication processes

–  Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, getting functional coverage collection using cover grou

– Experience with relevant CAD tools

 Requires US work authorisation

Keywords//: ASIC, FPGA, SoC, Verification, UVM, Design, CMOS, Cadence, Analog, Mixed-Signal, Digital, Semiconductor, Testbench, Digital

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