Senior Digital ASIC / FPGA IP Design Engineer

Senior Digital ASIC / FPGA IP Design Engineer

We are recruiting for Senior Digital ASIC / FPGA IP Design Engineer, who is experienced in VHDL and System Verilog for RTL design, to join leading company, based in Sweden, on a contract basis.

You are best suited for this position if you have;

• Extensive experience with troubleshooting and debugging in regression suite and automatic test bench environment.
• Considerably worked with VHDL and System Verilog for RTL design.
• In depth knowledge of the complete frontend design flow from the very beginning.
• Professional proficiency in oral and written English.
• The ability work autonomously, eagerly and diligently, even when working with insufficient information.
• Knowledge in data manipulation related algorithms is favored.
• Notable experience in System C/C++ and processor design is preferred.

Tagged as: ASIC, C++, Digital ASIC IP Designer, Digital FPGA IP Designer, FPGA, HDL, IP Design, processor design, RTL, Senior Digital ASIC / FPGA IP Design Engineer, System C, System verilog