Senior Digital IC Design Engineer – SoC/IP/RTL

Senior Digital IC Design Engineer – SoC/IP/RTL

My client is an exciting well-funded start-up working in Neuromorphic Computing for the extreme edge. They are looking for a Senior Digital IC Design Engineer to join and lead the architecture design and development of digital IP blocks within my clients upcoming SoCs.

Requirements for Senior Digital IC Design Engineer:

• Experience in SystemVerilog, Verilog, and/or VHDL
• Experience in designing signal processing, datapaths, interfaces, interconnects
• Knowledge of clock domain crossing (CDC) techniques, asynchronous design techniques
• Has strong experience with RTL design for ASIC targets
• Strong programming and scripting skills: MATLAB, Python, C/C++, Perl, Tcl
• Good experience in EDA tools such as simulators
• Experience in ASIC/FPGA/SoC system-level/top-level integration, DfT

Interested to know more?

Please get in touch at jd@eu-recruit.com.

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