SENIOR DIGITAL VERIFICATION ENGINEER (UVM, DSP, SYSTEM VERILOG, ASSER

SENIOR DIGITAL VERIFICATION ENGINEER (UVM, SYSTEM VERILOG, ASSERTION)

We are now hiring for a Verification Design Engineer – Verification of digital blocks and top level in digital domain of power management circuits for battery operated portable devices. The successful candidate will to join their expanding team in Sweden.

Intiailly on a 6 month contract with a very strong possibility of being extended.

The key skills required for the Verification Design Engineer role are:

• Several years of experience in digital verification
• Familiar with advanced verification techniques (e.g UVM/DSP/System Verilog/Assertions)
• Experience with constrained random verification of digital logic

In terms of education a master or above is ideal, however we will consider a bachelors.

Senior Digital Verification Engineer job using  UVM/DSP/System Verilog/Assertions

Key Words: Verification Design Engineer / UVM, System Verilog, Assertion / Digital Logic / Random Verification / RTL Coding / Germany / Munich / Permanent / Design / Digital / Senior / Verification.