SoC/ASIC Architect – ASIC / FPGA / SOC / RTL / VHDL / Verilog / Perl / Python

SoC/ASIC Architect – ASIC / FPGA / SOC / RTL / VHDL / Verilog / Perl / Python

SoC/ASIC Architect – ASIC / FPGA / SOC / RTL / VHDL / Verilog / Perl / Python

We are currently on the lookout for an experienced SoC/ASIC Architect for a global technology company in Lund, Sweden.

 

This 6 month contract role often gets extended and will pay well based on experience level. This is a remote position during covid but will be expected on site after, likely 2022.

 

You will be responsible for the ASIC/FPGA architecture definition, breaking down product requirements, IP selection, technical investigations and area, power, performance evaluation and optimization.

 

For this SoC/ASIC Architect position, I’m interested in speaking to people with the following:

  • RTL design and verification experience
  • VHDL, Verilog, System-Verilog and UVM experience
  • Chip timing budgeting/partitioning
  • Low power design experience
  • Scripting experience in Python, TCL and Perl

 

I welcome your application if you’d like to find out more and if you know someone it would suit, we offer a fantastic referral scheme which I would be happy to discuss.

 

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