SoC Design & Verification Engineer (SystemVerilog) – all levels

Our client is a global leading telecommunications company. Developing equipment for LTE and 5G communication systems. 

We have positions for all experience levels from 2 to 15 years. 

What are the responsibilities in this SoC Verification and Design role?

• Participate in outlining System-on-Chip system design and derive the SoC functional and design specific for SoC (ASIC/FPGA/low level SW) and IP functionality level 
• Preparation and review of functional and design specification for SoC/IP
• Algorithm and model design (Coding of SoC functionality from top-level down to block level)
• Verification and simulation – system emulation and bring-up on FPGA prototype 

What are the technical requirements in this SoC Verification and Design role?

• Minimum of 2 years experience in developing ASIC/FPGAs/Low level SW
• Excellent VHDL/Verilog know-how and many years of coding and modeling experience
• Good practices of SystemVerilog/UVM verification languages (C,C++ understanding would be beneficial)
• Complete understanding of the SoC (ASIC/FPGA/Low level SW) design flow and process 
• Fluency in English 

If you would like to have a confidential discussion please do get in touch. 

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