Staff Digital Verification Engineer (UVM)

Our client is a global leader in the development of Image Sensors for the automotive industry. They are looking for an experienced Digital Verification Engineer to join an established team designing and verifying digital front end CMOS imaging sensors/ASICs. The role will involve all aspects of Digital verification (UVM) from test plan creation, verification infrastructure development, test writing, design debug through metrics collection.

 What are the requirements for this Staff Verification Engineer (UVM)? 

• 5+ years of experience in verification using SystemVerilog/UVM at both module and system levels.
• Verilog, SystemVerilog including functional coverage and SystemVerilog assertions
• Scripting lanaguages (PERL, TCL, Unix shell)
• Experience of using simulators (Cadence preferred)
• Higher level programming (C, SystemC) would be advantageous but not essential

 Should you have experience and UVM Methodologies and be interested in a new career opportunity please do get in touch.

Due to the urgency of this position we are not able to consider candidates outside the EU. If this sounds like a position you could be interested in please send on your CV to jthompson@eu-recruit.com.

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