Verification Engineer – System Verilog / UVM / CPU / ASIC / Python / C++

Verification Engineer – System Verilog / UVM / CPU / ASIC / Python / C++

A British Semiconductor company working on processors for AI and Machine Learning are looking for a Verification Engineer to join them at their site in either Cambridge or Bristol. This can be on a remote basis initially.

Requirements for the Verification Engineer:

  • Degree in Electronics, Engineering, or related field (new graduates will be considered)
  • Experience of the Verification process in CPU or ASIC environments
  • Experience with System Verilog, Python, C++ and Linux
  • Experience with UVM, STA, LLVM, GCC, DVCS or SGE

If this sounds like the role for you, please attach your CV to your application

Key Words:

Verification Engineer / Verification/ CPU / ASIC / System Verilog / Linux / C++ / Python / AI / UVM / STA / LLVM / GCC / DVCS / SGE / DRMS / XML / XPath / XSLT / HTML / DOM / JavaScript / SQL / Machine Learning / Semiconductor

#AI & Machine Learning #Semiconductor

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