Verification Engineer – UVM / System Verilog / IP Verification –

Verification Engineer – UVM / System Verilog / IP Verification – Initial 6 month contract

A leading Telecoms company is looking for a Verification Engineer to join their offices based in Lund, Sweden. This is for an initial 6-month contract, with extension likely.

Requirements:

• Masters degree or similar level of experience
• Advanced user of System Verilog
• Advanced user of UVM tools and methodology for IP verification
• Significant experience in assertions, scoreboards and coverage refinement
• Excellent programming skills e.g. SV, VHDL etc.
• Good scripting skills using e.g. Python, TCL or Perl
• Experience working with Agile with methodologies
• Experience in system-level verification – beneficial
• Knowledge in programming with C, C++, System C – beneficial

If this sounds like the role for you, please attach a copy of your CV with your application for review

Keywords:

Verification Engineer / Verification Contract / System Verilog / UVM / IP Verification / SV / VHDL / Python / TCL / Perl / Agile / System-Level Verification / C / C++ / System C / Contractor / Contract

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