Verification engineer – UVM

Company Information:?

My client, based in Stockholm, Sweden,  is a multinational networking and telecommunications company. This is a very long-term freelancing contract with projects having been confirmed until 2020.

What are the requirements for the Verification Engineer ?

• Detailed experience in UVM & System Verilog
• Experience in Verification (4 years)
• Extensive experience of architecting and implementing verification test benches for complex IP /module level designs using structured and maintainable strategies.
• Desirable Skills;Video, CPU, GPU or Display verification experience

Keywords- Verification, Engineer, UVM, CPU, System Verilog, GPU