Analog Design Engineer

Analog Design Engineer – Brussels, Belgium 

TASKS FOR THE UPCOMING PROJECT
During FY25 the focus is on a Production Project for next generation imaging, with tasks ranging from feasibility studies to the design/verification/implementation of a sensor.
You will report to the Analog Design Manager and your work will cover the following type of tasks:

• You will work on R&D on image sensors and circuits: This will include full-cycle follow-up from conception to design to layout and verification on block and on top level.

• You will work with other members of the design team on the analysis, feasibility study, design, verification of image sensors.
• You will perform IC design of the analog IP blocks and chip.
• You will perform functional and characterization verifications from block to top level according to Sony design flow.
• You will provide feedback to layout engineers and/or perform layout activities from an analog design perspective using advanced technology.
• You will perform documentations on block and top level during and after the designs.
• You will communicate with multi-site design engineers.

QUALIFICATIONS

• You have a master’s degree in electrical engineering or similar by experience.
• Analytical mind with a strong commitment to quality as well as high team spirit and social skills as you will be working with design teams, hardware and software engineers to successfully complete challenging IC and sensor system design projects.

• 3-5 years of experience with the design of complex analog blocks such as ADC, DAC, PLL, bias generator, gain amplifiers, and comparators. Knowledge of image sensor functions a plus.

• Experience with the design of analog blocks including architectural analysis, noise, power, and area analysis, schematic entry and critical simulation analysis.
• Experience with the full design flow including Cadence layout from early schematics, area estimation, full layout, parasitic extraction, ECO implementation.
• Skilled with SPICE simulator types with deep knowledge of tradeoffs such as power modeling, SPICE and fast SPICE, noise, transient, and monte carlo simulations.
• Knowledge of simulation analysis of analog blocks including a deep understanding of basic (R/L/C/Tr) element fabrication process, simulation models and model accuracy.
• Experience with LVS / DRC at block and full chip level using tools like Assura and Calibre.
• You are familiar with full physical verification flow and tools.
• You are familiar with parasitic extraction using tools like Cadence QRC, Synopsys StarRC.
• You have experience with power analysis, IR drop measurement, power planning, top level layout of full chips.