HW/SW Codesign for Many-cores

Position: HW/SW Codesign Engineer – Many-Core Systems
Experience Level: 1–3 years
Contract Type: Fixed-term (CDD)
Duration: 6 months initially, extendable up to 2 years based on performance

Role Overview:
Contribute to hardware/software co-design for many-core chips, with a focus on communication acceleration. You’ll model hardware components, develop interfaces, and analyze performance data.

Key Responsibilities:

• Co-design hardware/software interfaces for many-core architectures

• Model hardware components in high-level simulators (e.g., GEM5)

• Develop drivers and libraries in C for HW/SW integration

• Run simulations, collect performance data, and analyze results (plots/tables)

Minimum Qualifications:

• Bachelor’s, Master’s, or PhD in Computer Science or Computer Engineering

• Strong programming skills in C and Python

• Experience in RTL or SystemC hardware modeling/design

• Knowledge of OS internals (scheduling, syscalls, interrupts, memory management)

• Understanding of CPU architecture, cache systems, and interconnects

Preferred Qualifications:

• Experience with GEM5 simulator

• Working knowledge of C++

• Proven research output (papers or patents) in HW/SW co-design for many-core SoCs

• Authorship of 5+ publications or patents related to many-core hardware design