Mixed Signal Verification Engineer

Mixed Signal Verification Engineer
based in either Lausanne, Switzerland, UK (Reading/Northampton), Germany (Dortmund), or Denmark. 

Key Responsibilities

• Verification plan tasks in analog/mixed signal environment related to high speed SerDes designs
• Debug and flag bugs with design team
• Enhance and develop new methodologies with the verification team and EDA vendors
• Document and track verification plan tasks, bug findings and methodology work

Skills

• Good scripting techniques
• Good understanding of fabrication process, process corners, simulation, and verification setup
• Very good knowledge on electrical and discrete test benches / solvers in terms of run time optimization
• Very good knowledge about simulation tools and debugging techniques
• Good understanding of revision control
• Good communication and reporting skills

Experience

• Experience on digital/mixed signal/analog verification: test bench design, connect modules, design electrical/discrete partitioning, UDN, wreal, compile and elaboration debug
• Experience in behavioral modelling, basic knowledge of analog building blocks
• Experience with simulator: fast analog solver e.g., Cadence APS, SpectreX / digital solver e.g., Cadence Xcelium
• Experience in constrained random testbench development
• Experience in System Verilog Assertions
• Experience with Cadence Ocean Script
• Experience with Cadence Virtuoso Framework: Schematic editor, Assembler, AMS
• Experience on high-speed communication systems such as SerDes would be a plus
• Good digital verification background with some Specman/SV UVM exposure and/or analog verification background

Education
Graduated in Electrical Engineering

Mixed Signal Verification Engineer
based in either Lausanne, Switzerland, UK (Reading/Northampton), Germany (Dortmund), or Denmark. 

Key Responsibilities

• Verification plan tasks in analog/mixed signal environment related to high speed SerDes designs
• Debug and flag bugs with design team
• Enhance and develop new methodologies with the verification team and EDA vendors
• Document and track verification plan tasks, bug findings and methodology work

Skills

• Good scripting techniques
• Good understanding of fabrication process, process corners, simulation, and verification setup
• Very good knowledge on electrical and discrete test benches / solvers in terms of run time optimization
• Very good knowledge about simulation tools and debugging techniques
• Good understanding of revision control
• Good communication and reporting skills

Experience

• Experience on digital/mixed signal/analog verification: test bench design, connect modules, design electrical/discrete partitioning, UDN, wreal, compile and elaboration debug
• Experience in behavioral modelling, basic knowledge of analog building blocks
• Experience with simulator: fast analog solver e.g., Cadence APS, SpectreX / digital solver e.g., Cadence Xcelium
• Experience in constrained random testbench development
• Experience in System Verilog Assertions
• Experience with Cadence Ocean Script
• Experience with Cadence Virtuoso Framework: Schematic editor, Assembler, AMS
• Experience on high-speed communication systems such as SerDes would be a plus
• Good digital verification background with some Specman/SV UVM exposure and/or analog verification background

Education
Graduated in Electrical Engineering