PPA / Physical Design Engineer

PPA/Physical Design Engineer

About The Role

You will have experience of Physical Design (PD) flows specifically experience of bringing a design through the full PD flow from netlist to GDS (Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization and DRC closure)

What are we looking for?

• Understanding of Floor planning, Placement, CTS, P&R
• Experience using different techniques for low power designs and UPF/CPF flows.
• Good understanding of Primetime STA tool and timing closure methodologies.
• Developing and implementing timing ECOs including effect on congestion/routing/power.
• Understanding of different power grid structure, clock tree, and low-power reduction implementation methods.
• Understanding of signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing.
• Understanding of Physical Verification, IR drop analysis, Formal Verification
• Experience in automation using Perl/Python and tcl and ability to develop/support flows related to floor planning, integration and design validation.
• Good communication skills and ability & desire to work in a cross-site cross-functional team environment.
• Experience using Physical Design tools from at least one of the following EDA tool vendors in advanced process nodes, Synopsys (ICC2/Fusion Compiler) or Cadence (Innovus).
• Experience using synthesis tools from at least one of the following EDA tool vendors in advanced process nodes, Synopsys (DC/Fusion Compiler) or Cadence (Genus).

Education & Experience

Bachelor’s degree in Science, Engineering, or related field.
• 5+ years ASIC design, verification, or related work experience.