Senior ADC IC Architect

Senior ADC IC architect

Job functions We’re seeking a Senior ADC IC architect who will define and drive the design of high-speed high-performance wideband Analog to Digital Converter (ADC) functions to be integrated into our next RF SoC product dedicated to the 5G Communication market. In close collaboration with the analog/mixed-signal, digital and layout engineers, and the silicon evaluation team, the candidate will be particularly involved in the architecture definition of the ADC including mixed-signal and/or fully digital calibration techniques, the definition of the sub-blocks specification, the floorplan strategy, and the test strategy.
The ADC IC architect will report to the CTO.

Work description:

• In close relation with the RF SoC architect, translate the customer requirement into an ADC specification (resolution, Noise Spectral Density, harmonic Distortion, SFDR).
• Benchmark Time-Interleaved ADC state of the art.
• Define the ADC architecture and the calibration techniques to meet the dynamic specification with the lowest power consumption.
• Work closely with the RF SoC architect and other designers to specify the interface
  characteristic.

• Define the specification of the AMS and digital sub-blocks of the ADC including
  calibration circuits.

• Create a high-level ADC behavioral model.
• Discuss with the layout team floor planning and an isolation strategy to protect the
  sensitive analog/RF portions of the ADC against the noisy aggressors.

• Contribute to the definition of a simulation strategy to validate the ADC performances
  and the calibration techniques with the rest of the ADC sub-blocks.

• In close collaboration with the silicon evaluation team, contribute to the definition of
  integrated test points/pattern, the evaluation plan and production test strategy.

• Participate to design reviews.
• Participate to characterization.
• Write documentation.

Qualification and Experience:

• MSc or PhD in Electrical Engineering or equivalent with at least 10 years of
  experience in designing and evaluating high-speed high-performance ADC functions.

• Experience in specifying time-interleaved Analog-to-Digital Converters in advanced
  CMOS process is mandatory.

• Experience in designing mixed-signal functions such as ADC and/or DAC is
  mandatory.

• Deep understanding of error mechanisms that affect the linearity and noise
  performance of time-interleaved ADC.

• Experience in the definition and implementation of calibration techniques to compensate
  for the interleaving spurs in time-interleaved ADC architectures.

• Experience in the definition and implementation of calibration techniques to compensate
  for the static and dynamic errors of a single-channel Nyquist-Rate ADC such as
  Pipeline, Pipelined-SAR and SAR architectures.

• Good understanding of digital and analog signal processing PRO/CONS to leverage
  the best of the two worlds.

• Very good vision of the entire analog & mixed-signal IC design flow.
• Strong leadership and communication skills to work with AMS, Digital and layout
  teams as well as the silicon evaluation team.

• Experience with product development cycles from concept to production.
• Team player with a critical attitude and sense of initiative.
• Fluent communication in English (oral and written) is a must