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Senior Digital Verification Engineers
Senior Digital Verification Engineer
Overview
Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, verify, modify, and evaluate semiconductor devices and components. Develops, modifies and evaluates electronic parts, components or integrated circuitry for hardware and other systems. Conducts experimental tests on equipment and evaluates results. Develops specifications for selecting components and equipment to use. May also review vendors’ abilities to support development. Emphasis on Design Verification.
Job Responsibilities:
- Responsible for the pre-silicon verification of IP modules, IP subsystems, and/or SoC top.
- Responsible for defining digital verification strategy and plan for SoC top or its sub-modules.
- Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP subsystem, SoC system.
- Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
- Responsible for developing, debugging and running C/C++, System Verilog or UVM based verification environment for RTL/netlist simulation.
- Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.
Job Qualifications:
- Bachelor’s degree or above in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines, with 8-12 years of experience.
- Understanding of SoC architecture and functionality
- Understanding of directed and constrained random verification methodology
- Good knowledge in UVM, Verilog, System Verilog, C/C++, Shell
- Good software programming skills are important therefore
- Good knowledge in Scripting like Perl, TCL or Python is a plus
- Good communication skills to interact with teams across the globe and work independently
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