Senior Design Verification Engineer – UVM / SystemVerilog / Verification / Test Planning / Simulation / Debug

Senior Design Verification Engineer

Austin, Texas – Hybrid

A global leading Semiconductor designer and manufacturer is looking for a Senior Design Verification Engineer to join them. This will be a permanent role, onsite or on a hybrid basis in Austin, Texas.

In this role you will work on defining and developing components for products such as automotive microprocessors, microcontrollers, and application processors.

Requirements for the Senior Design Verification Engineer:

• BSc or higher in Engineering, Computer Science or a related field
• 4+ years of experience in IP or SoC Design or Verification
• Experience with Verilog, SystemVerilog and UVM
• Verification skills with test planning, testcase, testbench, simulation and debug
• Programming with Python, C/C++, Perl etc is beneficial
• Design skills with RTL coding, synthesis, design documentation is beneficial

You must be based in America already to be considered for this role

If interested, please email arisbridger@eu-recruit.com

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