Verification Engineer – UK (UVM, System Verilog)
A great opportunity for Verification Engineers to join a British semiconductor company at their site in Cambridge, UK.
Responsibilities:
For this role, we are looking for experienced Verification Engineers who can contribute to all phases of the verification flow. This includes:
- Ownership of a specific area of a CPU project ranging from unit-level testbench development through to the overall verification methodology for a CPU project.
- Responsibility for producing test plans and verification strategies.
- Planning, tracking, and coordinating the tasks of you or your team to meet high quality goals at the planned time
- Ensuring the quality of the verification work done is of the expected standard
- Being part of verification improvement strategies across the CPU group and the wider verification community
- Evaluating and determining causality of different issues throughout the verification process per project.
Required Skills and Experience:
- Experience in designing and implementing verification environments for complex RTL designs
- Well-versed in the use of hardware verification languages e.g. SystemVerilog or Specman ‘e’
- Understanding of end-to-end verification processes, from test plan creation through to verification closure
- Ability to quickly understand and apply complex specification detail
- Understanding of the fundamentals of computer architecture, with an emphasis on pipelining, exception handling, memory systems
‘Nice to have’ Skills and Experience:
- Verification methodologies such as UVM
- Practical experience of working on microprocessor designs
- In-depth understanding of memory protection, memory translation, vector processing in CPUs, exception and interrupt handling.
- Understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioral functional models.
- Knowledge of assembly language , and/or C/C++
Visa support can be offered if required.
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