Mixed-Signal Verification Engineer

Mixed-Signal Verification Engineer / IC design / Verification / Belgium

We are recruiting on behalf of a premier IC Design company in Belgium that is currently building out its team and expanding into multiple offices. The mixed-signal verification engineer defines the strategy of mixed-signal verification and real-number modelling for all ASICs developed.

Responsibilities:

• Define the strategy of mixed-signal verification and real-number modelling together with the mixed-signal team

• Review and contribute to mixed-signal verification plan across projects

• Develop real-number behavioural models for analog/mixed-signal building blocks, perform modelling across projects (wreal and System Verilog real-number modelling). These models are used for mixed-signal verification.

• Assist in setting up and executing mixed-signal verification across projects

• Assist and train design engineers in real-number modelling tasks

• Perform evaluations of new tools/methods that can improve the methodology

• Interact with the CAD team to improve the flow

• Communicate efficiently with the project team to successfully complete the project

Competences:

• You have at least 5 years’ experience in behavioural modelling of analog blocks and are experienced in System Verilog Real-Number Modeling and mixed-signal simulators like Cadence Xcelium

• You have a good knowledge of Matlab and programming skills are an asset (e.g. Python)

• You have strong communication and reporting skills, also in English

• You have leadership skills enabling you to define and implement a company strategy

If you are interested, apply using the link or send your cv directly to me at gr@eu-recruit.com

– References are welcome

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