DFT (Design For Test) Engineer

DFT (Design For Test) Engineer

Overview

• SoC project for leading global semiconductor company – needs 5X DFT Engineer’s to come on site to their design center in Munich. You will be directly impacting functionality for millions of products worldwide. 

Responsibilities & Skills

• 5 + years DFT experience on complex chip design 
• ability to own entire DFT solutions in a chip design – you will be involved in all aspects of chip design.
• Working with chip DFT team to document processor DFT specifications and define the SOC-processor test interface
• Developing and implementing DFT architecture
• Implementing DFT infrastructure
• Working with the validation team to verify DFT implementations and implement design changes
• Generating structural test vectors, analyzing and improving coverage
• Working with designers on STA, physical, power and logical issues
• Working with test engineers to bring up test vectors on silicon

• Experience with STA constraints development and analysis for DFT modes and SDF simulations
• Ability to conduct experiments during silicon debug, gathering and analyzing; and utilize scripting to support efficient handling of ATE data.

Salary is completely dependent on candidate – they pay in the top percentile of market rates with comprehensive packages.

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Tagged as: DFT, SoC #LI-LG1, STA, Synthesis