Design Verification Engineer – RTL / Verilog / IP / SoC / ASIC / FPGA

Website European Recruitment

Design Verification Engineer – RTL / Verilog / IP / SoC / ASIC / FPGA

 

I am searching for RTL Designers and Verification Engineers for a client in France.

 

We are looking for driven engineers who have experience in RTL Design, IPs or SoC, HPC

 

Requirements

  • MSc or PhD in EE, computer Engineering etc.
  • 5+ years in Verilog or VHDL RTL Design or Verilog, System Verilog and Verification IPs
  • Experience in High speed interface protocols such as PCIe / CCIX / CXL / Gen-Z etc. Memory and HPC Systems.
  • Scripting languages such as Python, TCL, Cshell etc.
  • Background in Circuit design is beneficial
  • Must have relevant work permissions for France.

 

Key words: #Verification #RTLDesign / #Semiconductors / #Hardware / IPs / SoC / ASIC / FPGA / RTL / VHDL / Verilog / System Verilog / HPC / High Performance Computing / PCIe High-Speed / Serdes / PHY

 

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Categories: Semiconductor & Electronics

  Salary: Negotiable

  Location: Marseille, France

  Job type: Permanent, Full Time