DFT Engineer

Senior DFT Engineer

We are currently partnered with a leading Semiconductor Designer and Manufacturer based in France, who are looking for an experienced DFT Engineer to join their team.

Job Summary:

• Conducting top/block-level DFT insertion, including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG, and pattern simulation.
• Supplying SoC-level (top level) constraints and partitions for RTL/logic designers, floorplan and PD engineers, and DFT requirements.
• Verifying DFT circuitry and interfaces with other blocks, debugging timing simulation issues and working closely with the physical design team to generate and validate timing constraints.
• Being able to quickly understand problem statements and create solutions for DFT, diagnosis, and yield learning.

Skills required:

• 7+ years of DFT experience
• Solid fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST.
• Good experience with System Verilog, Perl/Tcl/Python scripting.

If this is of interest or you’d like some more information, please get in touch with me on:

Email: mn@eu-recruit.com

Phone: +44 (0) 3333071622

Mobile: +44 (0) 783 788 5469

Key Words: DFT / Design for Test