Digital Design Engineer – CONTRACT

Job Description:

• Using Verilog design and implement a compliant UICC slave interface compatible with ISO7816. This will be fabricated on an SoC to interface our CryptoIsland IP to an external cellular modem.
• Create Top and Testbench levels verification test benches using Verilog.
• Work together with a dedicated verification engineer to fully verify the IP prior to tapeout.
• Create design documentation describing and supporting the design.
• Work on a daily rate basis.

Key Skills:

• Extensive knowledge designing IP using Verilog.
• Familiarity with UVM / formal verification.
• Understand of Linting, Synthesis, CDC and DFT checks, required to implement production quality IP.
• Understanding of system issues such as clock domain crossing and low power techniques.
• Familiarity with simulators including Mentor Questasim, Synopsys VCS & Cadence Incisive.
• Familiarity with our IP would be advantageous but is not a pre-requisite.
• Familiarity with repository systems such as SVN would be beneficial. A basic understanding is required.

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Keywords: Digital / Design / Engineer / IP / Verilog / System Verilog / UVM / Fomal Verification / Linting / Synthesis / CDC / DFT / Mentor Questasim / Synopsys VCS / Cadence Incisive / SVN / SoC

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