Digital Design / Verification Engineer – (ASIC/DFT/System Verilog)

Digital IC Design / Digital Verification

We are looking for an experienced Digital Design Engineer to join a fabless semiconductor company who specialise in developing fully custom Integrated Circuits combined with management of the supply chain.

This role will based at the companies Headquarters in Grenoble, France.

Fantastic salaries and development opportunities! Visa support offered where required.

Responsibilities:

• Study, specify and design digital blocks, sub-systems (e.g. around an embedded processor or a memory sub-system…) and/or top level, making area/power estimations
• Elaborate testability insertion strategy corresponding to the circuit specifications
• Perform verification tasks (coverage rate, unit block simulation, complete system simulation, mixed analog / logic simulation, functional and test modes…) until the generation of test patterns for silicon measurements in our lab.
• Improve the digital design, functional and test mode verification flow
• Perform digital synthesis and Design for Test (DfT), using techniques that reduce the difficulty and cost associated when testing an integrated circuit (with the use on scan compression, built-in self-test (BIST) or increased observability using JTAG…)
• Lead, debate and present the choice of architectures and design status during review meetings within the ASIC project team and in front of customers.

Requirements:

• Engineering degree (or equivalent) in microelectronics
• 5 years in Front-end ASIC digital design in VHDL and/or Verilog and/or SystemVerilog, and in digital synthesis for DFT
• Comfortable in scripting (python, tcl, …)
• Experience with seeing a project through from beginning to completion with strong customer interaction
• Excellent analytical and problem-solving skills
• Ability to work independently but with a strong team spirit, while being a real force of proposals
• Curiosity, interest for final applications, rigor and requirement in the quality of work

Bonuses: Knowledge of different tools (Mentor, Synopsys, Cadence), design in different languages (SystemVerilog, VHDL, …), experience in mixed ASIC environment.

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