Digital IC Verification Engineer – VHDL/Verilog

Digital Verification Engineer – VHDL / Verilog / UVM

Location: Paris or Grenoble, France

We’re partnered with a fast-growing well-funded Semiconductor Company who is looking for a skilled ‘Digital Verification Engineer’ to join their team in either Paris or Grenoble, France.

This team focuses on complex mixed-signal ASICs, pushing the boundaries of technology and offering opportunities to work on projects that could have a significant impact.

Responsibilities:

• Establish and execute custom verification approaches to thoroughly test circuit functionality.
• Develop a comprehensive verification strategy aligned with circuit specifications.
• Craft self-contained test benches for individual blocks, subsystems, and the entire design, incorporating virtual intellectual property (VIPs).
• Automate regression testing on RTL and gate-level netlists, ensuring adherence to verification plans.
• Collaborate with the Analog design team to perform mixed-signal simulations.
• Actively participate in evaluating the manufactured ASIC within the measurement lab.
• Contribute to team efforts and ensure successful verification of this cutting-edge ASIC.

Skills:

• You have a MSc or PhD in Electrical Engineering or equivalent.
• 3+ years of hands-on experience in Verification activities.
• You have solid knowledge of a digital hardware description languages (VHDL or Verilog)
• You have solid knowledge of System Verilog
• Experience of UVM methodology is a plus

Interested to know more?

Apply here with your CV .

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