Digital Verification Engineer

Job Description:

• Work with design team to understand the design intent and bring up the verification plans and schedules
• Develop test environment, test plan, and test cases based on design specification and verification requirements
• Initiate test plan review and verification reviews with the teams at every stage
• Debug test cases and report verification result to achieve the expected code/functional coverage goal
• Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity
• Take dedicated ownership to execute block level and SOC level verification
• Drive the development of behavioral models for analog/MEMS blocks

Qualification:

• MSEE with 5+ years (or PhD with 2+ years) of digital functional verification experience on complex SoC or mixed-signal ASIC product development
• Conversant with some programmable languages such as Verilog, SystemVerilog, Perl/Python/Tcl scripts, Makefile and C++
• Experienced in Real Number Modeling in SystemVerilog or VerilogAMS language for discrete-time behavioural models of analog blocks
• Experienced with environment and flow build-up with OVM/UVM/VMM, Metric-Driven verification methodology
• Experienced with Assertions like PSL or SVA etc
• Experienced with simulation tools such as VCS or NC-Sim/irun
• Understanding assembly programming and firmware development

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Keywords: Digital / Functional / Verification / SoC / Mixed Signal / ASIC / Product Development / Verilog / System Verilog /  OVM / UVM / VMM / PSL / SVA / VCS / NC-Sim / Assembly Programming / Firmware Development

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