Digital Verification Engineer – UVM / VHDL / Verilog / TCL / Python

Digital Verification Engineer – UVM / VHDL / Verilog / TCL / Python – Expanding Semiconductor company – Growth Opportunities

I’m currently on the lookout for an experienced Digital Verification Engineer.

You will be working for a well funded, rapidly expanding, semiconductor company that has recently raised over €10 million in additional funding to fuel their growth.

For this role, you will work in a dynamic team of highly motivated engineers, and you will work on the verification of state of the art digital processing functions for ASIC with collaboration with digital IC and mixed signal. You will be defining and implementing verification methodologies, writing block and top level self checking benches, implementing regression tests on RTL and gate level netlists and participating in design reviews.

This is a permanent full time role with a preference to being on-site in either Paris, Caen or Grenoble, however, they said they may be open to discuss hybrid options on a case by case basis, but this will need to be within France.

For this Digital Verification Engineer position, I’m interested in speaking to people with the following:

– 3-4+ years experience in digital verification

– Good experience with System Verilog

– Experience with UVM is a bonus

– Knowledge of a digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)

I welcome your application if you’d like to find out more and if you know someone it would suit, we offer a fantastic referral scheme which I would be happy to discuss.

Keywords:

Semiconductor / Digital Verification / UVM / Python / System Verilog

#semiconductor #verification #uvm #systemverilog

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