Digital Verification Engineer – Visas Supported

Digital Verification Engineer

A fantastic opportunity for an experienced Digital Verification Engineer to join a Fabless Semiconductor company, who are an innovative leader in high-speed and energy efficient chip-chip link solutions.

You will work alongside a team whose work has a critical impact to the evolution of the electronics industry, continuously developing to meet customer demands.

**Choice of location in Dortmund (Germany), Lausanne (Switzerland) or Northampton (UK).

Key responsibilities

• Work with Design Engineers in verification and validation of circuit designs
• Prepare design verification plan based on design specifications
• Plan and schedule assigned projects for timely completion
• Utilize latest techniques, tools and technologies for design verification activities
• Maintain design verification environment, track and close design bugs
• Develop design verification methodologies and implement standard debug flows
• Participate in design reviews

Your profile

• 5+ years’ experience in the semiconductor industry.
• Bachelor of Engineering in Electronics and Electrical Engineer (or similar)
• Expert in digital design verification, using standardized methodologies, i.e. UVM
• Experience in simulating mixed signal designs with real-number Verilog behavioural models is highly desirable
• Familiarity with SerDes is highly desirable
• Experience with SystemVerilog Assertions (SVA) and formal verification is valuable
• Experience in constrained random testbench development
• Proven track record in verifying complex designs (preferably in high volume ASIC applications)
• Familiarity with high level protocols (e.g. PCIe, USB, DP) is an added bonus
• Very good knowledge on simulation tools and debugging techniques

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