IC Layout Engineer

IC Layout Engineer

Location: Paris, Grenoble or Caen

We’re partnered with a fast-growing well-funded Semiconductor Company who is looking for a skilled ‘IC Layout Engineer to join their team.

Their design team is seeking a dynamic and highly motivated Layout Engineer to work on physical implementation and verification of analog and mixed-signal ASIC functions to deliver state-of-the-art Integrated Circuit (IC) in deep submicron CMOS technology.

Responsibilities:

• Work with analog, mixed-signal, and digital designers to define the ASIC floorplan, sub-blocks, input/output pin placement, and top-level assembly.
• Physically implement high-speed and high-performance analog and mixed-signal blocks, including integrating digital macros.
• Optimize the layout to meet circuit area and performance requirements.
• Optimize the layout for voltage drop, matching, speed, and coupling.
• Perform sign-off physical verification of sub-blocks and/or the top chip to meet all manufacturing requirements (DRC, LVS, ERC, EM).
• Generate post-layout netlists with parasite extraction tools.
• Work as part of a team to design state-of-the-art integrated circuits.
• Prepare and participate in layout reviews.

Skills:

• You have at least 6 years of experience in integrated circuit (IC) development with a proven track record of successful tape-outs.
• You have experience in the development of an IC product from specifications to mass production.
• You have hands-on experience in mask design for analog and/or mixed-signal functions with strict requirements for matching, low parasitics, and low coupling.
• You have a solid understanding of the Cadence analog layout flow, including mask checks (LVS, DRC, ERC, EM).

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