Physical Design Engineer / Paris or Grenoble / RTL to GDS / Synthesis / P&R / STA

Physical Design Engineer / Paris or Grenoble / RTL to GDS / Synthesis / P&R / STA (m/f/d)

Location: Paris, Grenoble or Caen

A great opportunity for an experienced Physical Designer to join a a growing Semiconductor company, specializing in design and marketing of highly-integrated mixed-signal products.

The successful candidate will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market, alongside the team at you choice of location. (Paris, Grenoble or Caen)

Work description

• Responsible for the physical implementation from RTL to GDSII of a complex ASIC in advanced CMOS process (22nm and below technologies)
• Work closely with the RTL design team to understand the digital architecture and execute the physical design implementation
• Participate to the definition and development of the physical implementation flow
• Manage floorplan, pin placement, power planning and block/top level assembly
• Elaborate timing budget and write power intent (SDC) based on the design information and specification requirement
• Achieve timing and physical closure, including lithography optimizations
• Perform Quality Assurance checks (i.e., DRC, LVS, equivalence, power intent checking)
• Perform Quality of Result checks including signoff timing analysis and power analysis (IR drop, Electromigration checks, power consumption analysis)
• Integrate DFT scan
• Participate to the evaluation of the fabricated ASIC in our measurement lab
• Work in team to successfully design a state-of-the art ASIC

Qualification and Experience

• MSc or PhD in Electrical Engineering or equivalent
• 10+ years of hands-on experience in physical design of digital IC from RTL to GDSII
• Knowledge of scripting languages (TCL, Python, Bash, Make, Skill)
• A previous experience with Cadence physical design flow is mandatory
• Experience with the full RTL to GDS2 physical design flow execution (Synthesis, P&R, STA, DFT insertion, DRC and LVS sign-off) with 22nm and below technologies is mandatory.
• An Experience with large designs (>1M gates) with advanced CMOS technologies (22nm and below) and high clock speed (up to 1Ghz) is a plus
• A previous experience in physical implementation of digital processing functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers is a plus

You also can reach me for any questions on lh@eu-recruit.com

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