Physical Design Engineer- SDC Constraints

Physical Design Engineer – SDC Constraints

Opportunity to Join a global semiconducting organization that is a leading provider of high-speed, energy-efficient chip-to-chip link solutions are looking for a Physical Design Engineer to join their team in Germany on a permanent basis.

If This is, you please continue reading below!

Responsibilities

• Work closely with the Architecture and RTL team to ensure first-time-right high-volume silicon production
• Timing Constraints development, timing constraints validation, sign-off Static Timing Analysis and support for full chip & block-level timing closure will be the primary focus and responsibility
• Block and chip level STA with all aspects, reviewing and defining constraints with the design team, implementing SDC constraints to be used for block and chip (flat) STA, analyse violations and clean with help of frontend design and PD team
• Good knowledge of RTL to GDS implementation flow (synthesis, P&R, LEC, STA)

What’s in it for you

• Hybrid Working Options
• Promotion Guaranteed prospects
• Competitive Salary Package

Requirements

• Good scripting capabilities (shell, TCL, Python,)

• Experience in gathering and defining SDC constraints, specifically on top-level incl. DFT. Requires great team-work, tenacity, stamina and eye-for-detail. Also requires excellent communication and people skills to pull information from team members

• 10+ years’ experience in the semiconductor industry

• Experience on modern semiconductor process technologies such as, 28nm, 22 nm,16nm, 7nm, 3nm

• Expertise in Timing/SDC constraints generation and management

Keywords :-Python / Shell / RTL / STA /SDC

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