Physical Design Engineer – STA, Floorplanning, P&R

Physical Design Engineer – STA, Floorplanning, P&R

Description:

In this visible role, you will be taking part in the SoC physical design cycle from Netlist to Tapeout, including full flow of Back-end implementation and verification

Core Responsibilities:

• Physical Implementation of a complete SoC from netlist to tape-out
• Floor-planning, clock and power distribution , place & route
• Familiar with static timing closure with commercial tools
• Advantage: Power and noise analysis (EM/IR-Drop/Xtalk)
• Advantage: Layout verification (DRC/LVS)

Qualifications:

Experience in physical design of large scale SoC :

• Extensive experience with one of the place & route tools available today (Synopsys / Cadence). Familiar with hierarchical design approach, top-down design, timing and physical convergence
• In-depth understanding of static-timing analysis, extensive know-how in clock/power distribution and analysis, RC extraction and correlation.
• Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
• Scripting and programming experience using several of the following: Perl, TCL and Make
• Knowledge in Verilog – advantage

Education:

• MSEE or equivalent preferred

Keywords: physical design, implementation, DRC, LVS, STA, Timing analysis, Place & Route, RnR