Physical Design Engineer – STA / Static Timing Analysis / SDC Constraints / Timing Constraints Manager

Physical Design Engineer – STA / Static Timing Analysis / SDC Constraints / Timing Constraints Manager

• Do you have good exposure to SDC Constraints?
• Solid RTL to GDS implementation flow experience?
• Want to join leading company focused on providing efficient, high-speed, chip-to-chip link solutions?

We’re working with a well established organization with offices in multiples counties in Europe and they’re seeking a Physical Design Engineer to join their team in Dortmund in Germany on a permanent basis.

To be successful in this role, you should have a minimum of 5+ years experience in a Physical Design role, experience on modern semiconductor process technologies such as, 28nm, 22 nm,16nm, 7nm, 3nm and good SDC Constraints knowledge.

What’s in it for you?

You will receive a very good base salary, bonus, relocation and visa (if needed) assistance plus a good amount of hybrid working (2 days per week remote).

All this working within a diverse and multicultural team.

What we look for:

• Good knowledge of RTL to GDS implementation flow (synthesis, P&R, LEC, STA)
• Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
• Expertise in Timing/SDC constraints generation and management
• Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)
• Experience in gathering and defining SDC constraints, specifically on top-level incl. DFT. Requires great team-work, tenacity, stamina and eye-for-detail. Also requires excellent communication and people skills to pull information from team members.
• Flow development with focus on cross project reusability

Any of the following will be considered a plus:

• 10+ years’ experience in the semiconductor industry, with min. 5yrs in a technical Digital Physical Design role.
• Experience on modern semiconductor process technologies such as, 28nm, 22 nm,16nm, 7nm, 3nm
• User of EDA tools for design and verification such as, Cadence Tempus, Quantus (QRC), Genus and LEC, etc
• Experience in SDC verification tools – such as Fishtail
• Expertise in running hierarchical and flat static timing analysis incl. cross talk SI/glitch analysis

If this sounds interesting and you’d like to learn more, click the link below to apply or email me with a copy of your resume on smouland@eu-recruit.com

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