Senior Design Verification Engineer / UVM / Hybrid

Senior Digital Verification Engineer / UVM / Test Plan / Milan / Italy / Hybrid

We are seeking a talented design verification engineer to work alongside the analog, mixed-signal and digital design teams. You will be working on the model-based design flows for digital signal processing applications.

Experience required:

• Digital Test plans
• Working in a UVM-SV test environment
• Verification of signal processing
• SystemVerilog, MATLAB, Simulink, Python

For this role, you must be located in Milan and be able to be onsite. They are offering 2-3 weeks per month of remote working, but it is required you are in commutable distance of the office.

This is an urgent hire.

If interested in this role please apply here or send your email direct to gr@eu-recruit.com

Feel free to refer someone you think is great!

Verification / UVM / Engineering / Semiconductor / Automotive / MATLAB / Italy / Milan / Digital Design / Onsite / Hybrid

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