Senior DFT Engineer / MBIST Expert

Senior DFT Engineer / MBIST Expert

European Recruitment

Are you a DFT engineer with strong experience in MBIST that is looking for a new role at an exciting and highly funded European fabless semiconductor company?

At European Recruitment we are currently working alongside a highly innovative Paris based hardware company, helping them to bring on board a Senior DFT Engineer.

Responsibilities:

  • Responsible for the DFT architecture and drive and execute the DFT implementation of a complex SOC in advanced CMOS process (sub 20nm technologies).
  • Responsible for the development of a DFT flow (HW DFT insertion, test vectors generation, validation).
  • Responsible for the analysis of digital DFT metrics of proposed DFT solutions in view of the DFT requirements (test time, yield and default rate).
  • Advise digital design engineers on designing testable functional modules.
  • Work closely with the RTL design team, physical implementation team to ensure a seamless integration of DFT features without impact the SOC performances.
  • Work closely with the industrialization team to define the optimum DFT solution (test time, yield) and provide the ATPG test vectors for production testing.
  • Work in team to successfully design a state-of-the art SOC.
  • Participate to design reviews.
  • Write documentation in accordance with company QA policy.

Qualifications:

  • You have a MSc or PhD in Electrical Engineering or equivalent and hands-on experience in DFT implementation in complex digital and/or SOC circuits.
  • You have good knowledge in RTL design.
  • You have knowledge of scripting languages (TCL, Perl, Python).
  • You have hands-on experience with ATPG, MBIST, ECC and Redundancy.
  • You have hands-on experience with ASIC test methods (Iddq, delay test, very low voltage test) and on silicium physical and electrical defects (stuck-at, brieging…)
  • You have a strong knowledge of JTAG (IEEE1149.1, IEEE1149.3), logic tests (boundary scan, ATPG) and memory tests.
  • A previous experience with Cadence DFT design flow is a strong plus (Genus, Modus)
  • An experience with large designs (>1M gates) with advanced CMOS technologies (22nm and below) is a plus
  • You demonstrate good analytical and problem-solving skills
  • You are a team player with a critical attitude and sense of initiative
  • You communicate fluently in English (oral and written

If interested in this role please apply here or send your email direct to je@eu-recruit.com

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