Senior Digital IC Verification Engineer – UVM / SystemVerilog / DSP / MCU

Senior Digital IC Verification Engineer – UVM / SystemVerilog

(Onsite in Neuchatel, Switzerland)

I am looking for a Senior Verification engineer to define the verification strategy and plans for blocks and systems.

Key responsibilities

• Develop SystemVerilog/UVM environments for blocks and top-level SoCs.
• Debug functional errors in RTL.

The successful candidate will join a global team developing MCU and DSP systems as well as hardware accelerators that are used in variety of different products and markets.

Qualifications

• Degree in Electrical Engineering or similar
• Minimum 8 years of digital verification experience.
• In-depth knowledge and industry experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion based verification, test environment architecture & creation, regression management, coverage collection.
• Eligibility to work in Switzerland. (EU national / Citizen)

Bonus Skills:

• Project/task leadership
• Verification of signal processing components
• Verification of MCU systems
• 3rd party verification IP deployment
• Programming skills – Python, Tcl, embedded software

Interested to know more?

Apply here with your CV or get in touch at:

cp@eu-recruit.com

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