Senior Digital Verification Engineer – Cadence – UVM – Semiconductors

Senior Digital Verification Engineer – Cadence – UVM – Semiconductors

The company

We are proud to be partnered with a global leader in Power and Sensing solutions for motion control and energy-efficient systems. With more than 50+ years of experience, their innovations are helping customers in advanced mobility, green energy, and factory automation.

The role

They are looking for a Senior Digital Verification Engineer to join their expanding team in Milan. You will be using cutting-edge tools to verify state-of-the-art products in their Model-Based Design flow for digital signal processing applications.

About you

• Bachelor’s / Master’s degree of 5+ / 3+ years of experience in Digital Design and/or Verification.
• Knowledge of SystemVerilog and UVM is a must.
• Experience with the usage of Jama, MATLAB/Simulink, Python is a strong plus.

If you feel you have the skills above, I would love to hear from you and discuss the opportunity in more detail, please contact me at rs@eu-recruit.com with your CV to arrange an initial call.

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