Senior Layout Engineer – (Semiconductor/CMOS Technology)

Layout Engineer

(Option to be based in Paris, Grenoble or Caen)

We are looking for an experienced Layout Engineer to join a Fabless Semiconductor company who specialize in the design and marketing of highly-integrated mixed-signal products.

In this role you will work on the physical implementation and verification of analog and mixed-signal ASIC functions to deliver state-of-the-art Integrated Circuit (IC) in deep submicron CMOS technology.

Work description

• In close collaboration with analog, mixed-signal and digital designers, define the ASIC floorplan and its sub-blocks, input / output pin placement and top-level assembly
• Full-custom physical implementation of high speed and high performance analog, mixed-signal blocks including integration of digital macros.
• Optimize the layout to meet circuit area and performance requirements
• Optimize the layout with respect to voltage drop, matching, speed and coupling.
• Perform sign-off physical verification of sub-blocks and/or top chip meeting all manufacturing requirements (DRC, LVS, ERC, EM)
• Generate post-layout netlist with parasite extraction tools
• Prepare / participate in layout reviews
• Respect and execute the development steps in accordance with the company’s development methodology.

Qualification and Experience

• 6+ years of experience in the integrated circuit development with successful tape-out track record.
• You have participated to the development of an IC product from specifications to mass production
• Hands-on experience in mask design for analog and / or mixed signal functions with strong matching, low parasitic, low coupling requirements.
• Solid knowledge of Cadence analog layout flow including mask checks (LVS, DRC, ERC, EM)
• You are a team player with a critical attitude and sense of initiative
• You are a professional who can deliver high-quality work on tight schedules

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