Senior Layout Engineer

Senior Layout Engineer

Location: Paris or Grenoble, France

We’re partnered with a fast-growing well-funded Semiconductor Company who is looking for a ‘Senior Layout Engineer’ to join their team in either Paris or Grenoble, France.

Work description:

• In close collaboration with analog, mixed-signal and digital designers, define the ASIC floorplan and its sub-blocks, input / output pin placement and top-level assembly
• Full-custom physical implementation of high speed and high performance analog, mixed-signal blocks including integration of digital macros.
• Optimize the layout to meet circuit area and performance requirements
• Optimize the layout with respect to voltage drop, matching, speed and coupling.
• Perform sign-off physical verification of sub-blocks and/or top chip meeting all manufacturing requirements (DRC, LVS, ERC, EM)
• Generate post-layout netlist with parasite extraction tools
• Work in team to design a state-of-the-art integrated circuit
• Prepare / participate in layout reviews

Qualification and Experience:

• You have experience in the IC development Layout
• You have participated to the development of an IC product from specifications to mass production
• Hands-on experience in mask design for analog and / or mixed signal functions with strong matching, low parasitic, low coupling requirements.
• Solid knowledge of Cadence analog layout flow including mask checks (LVS, DRC, ERC, EM)

Interested to know more?

Apply here with your CV .

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